The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a recess pattern in a semiconductor device.
As semiconductor devices become highly integrated, a gate channel length has decreased and an ion implantation doping concentration has increased in a method for forming a typical planar gate in which a gate is formed over a planarized active region. Thus, a junction leakage current is generated by an increased electric field. Therefore, it has become difficult to secure a refresh characteristic of a device.
To overcome aforementioned limitations, a recess gate process including a gate line formation method in which an active region of a substrate is etched into a recess pattern and a gate is then formed has been performed. Using the recess gate process reduces the channel length increase and the ion implantation doping concentration. Thus, the refresh characteristic is improved.
FIG. 1 illustrates a micrographic view of a typical recess pattern in a semiconductor device. An isolation structure 12 is formed in a substrate 11 to define active regions. The active regions are formed in a direction along a major axis. The active regions include line type recess patterns 14 formed in a direction along a minor axis. A method for forming the recess patterns 14 is described in FIGS. 2A to 2C.
FIGS. 2A to 2C illustrate cross-sectional views of a typical method for fabricating a recess pattern in a semiconductor device. The same or like reference numerals used for the descriptions in FIG. 1, FIGS. 2A to 2C, and FIG. 3 represent the same or like elements for convenience of description.
Referring to FIG. 2A, an isolation structure 12 is formed in a substrate 11 to define an active region. A mask pattern 13 is formed over the resultant structure, the mask pattern 13 exposing recess pattern regions. The mask pattern 13 is formed in a line type structure and formed over the substrate 11 with a uniform spacing distance. The mask pattern 13 is formed over the isolation structure 12 as well as the active region.
Referring to FIG. 2B, the substrate 11 is etched using the mask pattern 13 as an etch mask to form recess patterns 14. Reference numeral 12A refers to a remaining isolation structure 12A.
Referring to FIG. 2C, a gate insulation layer 15 is formed over the surface profile of the resultant structure. Gate patterns are formed in a manner that a portion of the gate patterns is filled in the recess patterns 14 and the rest of the gate patterns protrude above the substrate 11. Each gate pattern includes a stack structure configured with a gate electrode 16 and a gate hard mask 17.
In the typical method, the recess patterns 14 are formed over both the isolation structure 12 and the active region of the substrate 11. A gate line width has decreased to 70 nm or less as the design rule becomes finer. Thus, patterning for securing a small space of 40 nm or less is required.
The typical method forms the recess patterns 14 in a small space, and thus, a portion of the substrate 11 adjacent to the isolation structure 12 may be damaged (as shown with reference numeral 100 in FIG. 1). Consequently, a coupling 200 results between the active region and the gate pattern. A cell transistor may not operate due to the coupling 200. FIG. 3 illustrates a micrographic view of the coupling 200 generated during the typical method for forming the recess pattern in the semiconductor device.
Such a limitation makes a device process difficult to perform, and mass production may decrease due to a low process margin. Also, the mask pattern for forming the recess patterns is often required to include argon fluoride (ArF) photoresist layer, which is elaborate and expensive, due to the finer design rule.